The present application relates to contact structures for semiconductor devices, and more particularly, to multi-level contact structures with reduced contact resistance.
Multiple middle-of-line (MOL) contact levels have been employed at the 7 nm node to provide wiring flexibility for system-on-chip (SOC) applications. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers. Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is needed, a first lower end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end is connected to a respective interconnect structure in the metallization layer. A interconnect/contact structure at a single contact level typically includes a contact conductor portion and a contact liner/barrier present along the sidewalls and bottom surface of the contact conductor portion to prevent the diffusion of metal ions into surrounding dielectric materials. However, the presence of the contact liner/barrier at the interfaces between these multiple contact levels can lead to an increase in contact resistance and an overall increase in parasitic resistance. A method that allows reducing contact resistance in multi-level contact structures remains needed.